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Electrical vias in silicon and glass wafers

Electrical vias in silicon and glass wafers

Plan Optik AG draws on an exceptional technology to combine glass and silicon in multifarious ways in regards to the fabrication of sophisticated substrates for MEMS and optoelectronics applications. The specific properties of glass, especially the optical transparency and electrical insulation, are used for MEMS fabrication to realize most diverse devices in all fields of micro technology right from the start. Plan Optik offers silicon-glass-compound wafers, which allow the combination of both materials in the same wafer to take advantage of each material. Plan Optik is able to fabricate e.g. silicon wafers with glass inlets, which are used as optical window or as insulating ground for RF parts. The surface of such kind of wafers is similar to standard silicon wafers and is characterized by low ttv and roughness. The mixture of silicon and glass can vary in a very large range. Silicon wafers with glass inlets as well as glass wafers with silicon inlets can be produced. The structure shape and arrangement is almost free of design rules. The minimum structure size is limited to about 50 microns and the typical wafer thickness is in the range of 200 to 500 microns.

A special type of silicon-glass-compound wafers are wafers with electrical via's. In this case highly doped silicon is used to realize conductive vias through the substrate with a possible electrical resistance less than 1 Ohm. In general, three types of such wafers can be realized:

  • Silicon wafers with single vias, whereby each via is insulated by a surrounding glass bushing
  • Silicon wafers with larger glass areas including several via's
  • Glass wafers with highly doped silicon via's (shown in picture)

The main application of these electrical via wafers is waferlevel packaging (WLP) of MEMS devices. The via wafer is used as a cap wafer to combine vacuum tight encapsulation and vertical electrical connection of all devices on the wafer simultaneously.